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the nb7v33m is a differential divide by 4 clock divider with asynchronous reset. the differential clock inputs incorporate internal 50-ohm termination resistors and will accept lvpecl, cml and lvds logic levels. the nb7v33m produces a div 4 output copy of an input clock operating up to 10ghz with minimal jitter. the reset pin is asserted on the rising edge. upon powerup, the internal flip-flops will attain a random state. the reset allows for the synchronization of multiple nb7v33ms in a system. the 16ma differential cml output provides matching internal 50-ohm termination which provides 400mv output swing when externally receiver terminated with 50-ohm to vcc.


  • clock divider
  • ate, instrumentation
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