differential clock divider evaluation border-凯发登录

the nb7v33m is a differential divide by 4 clock divider with asynchronous reset. the differential clock inputs incorporate internal 50-ohm termination resistors and will accept lvpecl, cml and lvds logic levels. the nb7v33m produces a div 4 output copy of an input clock operating up to 10ghz with minimal jitter. the reset pin is asserted on the rising edge. upon powerup, the internal flip-flops will attain a random state. the reset allows for the synchronization of multiple nb7v33ms in a system. the 16ma differential cml output provides matching internal 50-ohm termination which provides 400mv output swing when externally receiver terminated with 50-ohm to vcc.
特性和应用

特性

  • clock divider
  • ate, instrumentation
评估/开发工具信息
产品 状况 compliance 简短说明 所用产品 行动
active
pb-free
differential clock divider evaluation border

your request has been submitted for approval.
please allow 2-5 business days for a response.
you will receive an email when your request is approved.
request for this document already exists and is waiting for approval.